SOI technology differs from traditional bulk semiconductor technologies in that the active semiconductor material of SOI technologies is typically much thinner than that utilized in bulk technologies. The active semiconductor material of SOI technologies will typically be formed as a thin film over an insulating material (typically oxide), with exemplary thicknesses of the semiconductor film being less than or equal to 2000 Å. In contrast, bulk semiconductor material will typically have a thickness of at least about 200 microns. The thin semiconductor of SOI technology can allow higher performance and lower power consumption to be achieved in integrated circuits than can be achieved with similar circuits utilizing bulk materials.
An exemplary integrated circuit device that can be formed utilizing SOI technologies is a so-called thin film transistor (TFT), with the term “thin film” referring to the thin semiconductor film of the SOI construction. In particular aspects, the semiconductor material of the SOI construction can be silicon, and in such aspects the TFTs can be fabricated using recrystallized amorphous silicon or polycrystalline silicon. The silicon can be supported by an electrically insulative material (such as silicon dioxide), which in turn is supported by an appropriate substrate. Exemplary substrate materials include glass, bulk silicon and metal-oxides (such as, for example, Al2O3). If the semiconductor material comprises silicon, the term SOI is occasionally utilized to refer to a silicon-on-insulator construction, rather than the more general concept of a semiconductor-on-insulator construction. However, it is to be understood that in the context of this disclosure the term SOI refers to semiconductor-on-insulator constructions. Accordingly, the semiconductor material of an SOI construction referred to in the context of this disclosure can comprise other semiconductive materials in addition to, or alternatively to, silicon; including, for example, germanium.
A problem associated with conventional TFT constructions is that grain boundaries and defects can limit carrier mobilities. Accordingly, carrier mobilities are frequently nearly an order of magnitude lower than they would be in bulk semiconductor devices. High voltage (and therefore high power consumption), and large areas are utilized for the TFTs, and the TFTs exhibit limited performance. TFTs thus have limited commercial application and currently are utilized primarily for large area electronics.
Various efforts have been made to improve carrier mobility of TFTs. Some improvement is obtained for devices in which silicon is the semiconductor material by utilizing a thermal anneal for grain growth following silicon ion implantation and hydrogen passivation of grain boundaries (see, for example, Yamauchi, N. et al., “Drastically Improved Performance in Poly-Si TFTs with Channel Dimensions Comparable to Grain Size”, IEDM Tech. Digest, 1989, pp. 353-356). Improvements have also been made in devices in which a combination of silicon and germanium is the semiconductor material by optimizing the germanium and hydrogen content of silicon/germanium films (see, for example, King, T. J. et al, “A Low-Temperature (<=550° C.) Silicon-Germanium MOS TFT Technology for Large-Area Electronics”, IEDM Tech. Digest, 1991, pp. 567-570).
Investigations have shown that nucleation, direction of solidification, and grain growth of silicon crystals can be controlled selectively and preferentially by excimer laser annealing, as well as by lateral scanning continuous wave laser irradiation/anneal for recrystallization (see, for example, Kuriyama, H. et al., “High Mobility Poly-Si TFT by a New Excimer Laser Annealing Method for Large Area Electronics”, IEDM Tech. Digest, 1991, pp. 563-566; Jeon, J. H. et al., “A New Poly-Si TFT with Selectively Doped Channel Fabricated by Novel Excimer Laser Annealing”, IEDM Tech. Digest, 2000, pp. 213-216; Kim, C. H. et al., “A New High-Performance Poly-Si TFT by Simple Excimer Laser Annealing on Selectively Floating a Si Layer”, IEDM Tech. Digest, 2001, pp. 753-756; Hara, A. et al, “Selective Single-Crystalline-Silicon Growth at the Pre-Defined Active Regions of TFTs on a Glass by a Scanning CW Layer Irradiation”, IEDM Tech. Digest, 2000, pp. 209-212; and Hara, A. et al., “High Performance Poly-Si TFTs on a Glass by a Stable Scanning CW Laser Lateral Crystallization”, IEDM Tech. Digest, 2001, pp. 747-750). Such techniques have allowed relatively defect-free large crystals to be grown, with resulting TFTs shown to exhibit carrier mobility over 300 cm2/V-second.
Another technique which has shown promise for improving carrier mobility is metal-induced lateral recrystallization (MILC), which can be utilized in conjunction with an appropriate high temperature anneal (see, for example, Jagar, S. et al., “Single Grain TFT with SOI CMOS Performance Formed by Metal-Induced-Lateral-Crystallization”, IEDM Tech. Digest, 1999, p. 293-296; and Gu, J. et al., “High Performance Sub-100 nm Si TFT by Pattern-Controlled Crystallization of Thin Channel Layer and High Temperature Annealing”, DRC Conference Digest, 2002, pp. 49-50). A suitable post-recrystallization anneal for improving the film quality within silicon recrystallized by MILC is accomplished by exposing recrystallized material to a temperature of from about 850° C. to about 900° C. under an inert ambient (with a suitable ambient comprising, for example, N2). MILC can allow nearly single crystal silicon grains to be formed in predefined amorphous-silicon islands for device channel regions. Nickel-induced-lateral-recrystallization can allow device properties to approach those of single crystal silicon.
The carrier mobility of a transistor channel region can be significantly enhanced if the channel region is made of a semiconductor material having a strained crystalline lattice (such as, for example, a silicon/germanium material having a strained lattice, or a silicon material having a strained lattice) formed over a semiconductor material having a relaxed lattice (such as, for example, a silicon/germanium material having a relaxed crystalline lattice). (See, for example, Rim, K. et al., “Strained Si NMOSFETs for High Performance CMOS Technology”, VLSI Tech. Digest, 2001, p. 59-60; Cheng, Z. et al., “SiGe-On-Insulator (SGOI) Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation” 2001 IEEE SOI Conference Digest, October 2001, pp. 13-14; Huang, L. J. et al., “Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding”, VLSI Tech. Digest, 2001, pp. 57-58; and Mizuno, T. et al., “High Performance CMOS Operation of Strained-SOI MOSFETs Using Thin Film SiGe-on-Insulator Substrate”, VLSI Tech. Digest, 2002, p. 106-107.)
The terms “relaxed crystalline lattice” and “strained crystalline lattice” are utilized to refer to crystalline lattices which are within a defined lattice configuration for the semiconductor material, or perturbed from the defined lattice configuration, respectively. In applications in which the relaxed lattice material comprises silicon/germanium having a germanium concentration of from 10% to 60%, mobility enhancements of 110% for electrons and 60-80% for holes can be accomplished by utilizing a strained lattice material in combination with the relaxed lattice material (see for example, Rim, K. et al., “Characteristics and Device Design of Sub-100 nm Strained SiN and PMOSFETs”, VLSI Tech. Digest, 2002, pp. 98-99; and Huang, L. J. et al., “Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding”, VLSI Tech. Digest, 2001, pp. 57-58).
Performance enhancements of standard field effect transistor devices are becoming limited with progressive lithographic scaling in conventional applications. Accordingly, strained-lattice-channeled field effect transistors on relaxed silicon/germanium offers an opportunity to enhance device performance beyond that achieved through conventional lithographic scaling. IBM recently announced the world's fastest communications chip following the approach of utilizing a strained crystalline lattice over a relaxed crystalline lattice (see, for example, “IBM Builds World's Fastest Communications Microchip”, Reuters U.S. Company News, Feb. 25, 2002; and Markoff, J., “IBM Circuits are Now Faster and Reduce Use of Power”, The New York Times, Feb. 25, 2002).
Although various techniques have been developed for substantially controlling nucleation and grain growth processes of semiconductor materials, grain orientation control is lacking. Further, the post-anneal treatment utilized in conjunction with MILC can be unsuitable in applications in which a low thermal budget is desired. Among the advantages of the invention described below is that such can allow substantial control of crystal grain orientation within a semiconductor material, while lowering thermal budget requirements relative to conventional methods. Additionally, the quality of the grown crystal formed from a semiconductor material can be improved relative to that of conventional methods.
The methods described herein can be utilized in numerous applications, and in specific applications are utilized in forming static random access memory (SRAM) devices.
FIG. 1 shows a prior art six transistor static read/write memory cell 710 such as is typically used in high-density SRAMs. A static memory cell is characterized by operation in one of two mutually-exclusive and self-maintaining operating states. Each operating state defines one of the two possible binary bit values, zero or one. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a “high” voltage to indicate a “set” operating state. The memory cell output produces a “low” voltage to indicate a “reset” operating state. A low or reset output voltage usually represents a binary value of zero, while a high or set output voltage represents a binary value of one.
Static memory cell 710 generally comprises first and second inverters 712 and 714 which are cross-coupled to form a bistable flip-flop. Inverters 712 and 714 are formed by n-channel driver transistors 716 and 717, and p-channel load transistors 718 and 719. In a standard bulk silicon implementation, driver transistors 716 and 717 are typically n-channel metal oxide silicon field effect transistors (MOSFETs) formed in an underlying silicon semiconductor substrate. P-channel load transistors 718 and 719 are typically arranged in a planar bulk implementation, are formed to extend in an n-well adjacent the n-channel FETS, and are interconnected to the n-channel FETs in accordance with standard CMOS technology.
The source regions of driver transistors 716 and 717 are tied to a low reference or circuit supply voltage 715 (labeled VSS in FIG. 1), which is typically referred to as “ground.” Load transistors 718 and 719 are connected in series between a high reference or circuit supply voltage 711 (labeled VCC in FIG. 1) and the drains of the corresponding driver transistors 716 and 717, respectively. The gates of load transistors 718 and 719 are connected to the gates of the corresponding driver transistors 716 and 717 through interconnects 725 and 727.
Inverter 712 has an inverter output 720 formed at the common node 731. Similarly, inverter 714 has an inverter output 722 at the common node 733. Inverter 712 has an inverter input 725 at the common gate node, with the input 725 being connected to an interconnect 724. Inverter 714 has an inverter input 727 at the common gate node, with the input 727 being connected to an interconnect 726.
The inputs and outputs of inverters 712 and 714 are cross-coupled to form a flip-flop having a pair of complementary two-state outputs. Specifically, inverter output node 731 is cross-coupled to inverter input node 727, and inverter output node 733 is cross-coupled to inverter input node 725. In this configuration, inverter outputs 720 and 722 form the complementary two-state outputs of the flip-flop.
Node 731 represents the common node of electrical interconnection between source/drain regions of CMOS transistor pairs 716 and 718 of inverter 712. Similarly, node 733 represents the common node of electrical interconnection between the source/drain regions of transistor pairs 717 and 719 of inverter 714. Nodes 731 and 733 can be referred to as common node contacts. Similarly, nodes 725 and 727 can be referred to as common gate contact nodes of the respective invertors 712 and 714.
A memory flip-flop, such as that described, typically forms one memory element of an integrated array of static memory elements. A plurality of access transistors, such as access transistors 730 and 732, are used to selectively address and access individual memory elements within the array. Access transistor 730 has one active terminal connected to cross-coupled inverter output 720. Access transistor 732 has one active terminal connected to cross-coupled inverter output 722. A plurality of complementary column line pairs, such as the single pair of complementary column lines 734 and 736 shown, are connected to the remaining active terminals of access transistors 730 and 732, respectively, at the shown nodes 713 and 721. Lines 734 and 736 can be referred to as a bit line and an inverted bit line (bit-bar) respectively. A row line (also referred to as a wordline) 738 is connected to the gate nodes of access transistors 730 and 732, at 718 and 719, respectively.
Reading static memory cell 710 involves activating row line 738 to connect inverter outputs 720 and 722 to column lines 734 and 736. Writing to static memory cell 710 involves first placing selected complementary logic voltages on column lines 734 and 736, and then activating row line 738 to connect those logic voltages to inverter outputs 720 and 722. This forces the outputs to the selected logic state “one” or “zero”, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
FIG. 2 shows an alternative four transistor, dual wordline, prior art static read/write memory cell 750 such as is typically used in high-density static random access memories. Static memory cell 750 comprises n-channel pull down (driver) transistors 780 and 782 having drains respectively connected to pull up load elements or resistors 784 and 786. Transistors 780 and 782 are typically n-channel metal oxide silicon field effect transistors (NMOSFETs) formed in an underlying silicon semiconductor substrate.
The source regions of transistors 780 and 782 are tied to a low reference or circuit supply voltage, labeled VSS and typically referred to as “ground.” Resistors 784 and 786 are respectively connected in series between a high reference or circuit supply voltage, labeled VCC, and the drains of the corresponding transistors 780 and 782. The common node 772 of the resistor(786)-transistor (782) pair is connected to the gate of transistor 780 by line 776 for cross-coupling. Similarly, the common node 768 of the resistor (784)-transistor (780) pair is connected to the gate of transistor 782 for cross-coupling by line 774. Thus is formed a flip-flop having a pair of complementary two-state outputs.
A memory flip-flop, such as that of FIG. 2, typically forms one memory element of an integrated array of static memory elements. A plurality of access transistors, such as access transistors 790 and 792, are used to selectively address and access individual memory elements within the array. Access transistor 790 has one active terminal connected to the common node 768. Access transistor 792 has one active terminal connected to the common node 772. A plurality of complementary column line pairs, such as the single pair of complementary column lines 752 and 754 shown, are connected to the remaining active terminals of access transistors 790 and 792, respectively. A row line 756 is connected to the gates of access transistors 790 and 792.
Reading static memory cell 750 involves activating row line 756 to connect outputs 768 and 772 to column lines 752 and 754. Writing to static memory cell 750 involves first placing selected complementary logic voltages on column lines 752 and 754, and then activating row line 756 to connect those logic voltages to output nodes 768 and 772. This forces the outputs to the selected logic state “one” or “zero”, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed. An advantage of the four-transistor SRAM cell is lower power consumption while an advantage of the six-transistor SRAM cell is higher performance.
A static memory cell is said to be bistable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to the operating state of the memory cell, as long as the memory cell receives power.
The two possible output voltages produced by a static memory cell correspond generally to upper and lower circuit supply voltages. Intermediate output voltages, between the upper and lower circuit supply voltages, generally do not occur except for during brief periods of memory cell power-up and during transitions from one operating state to the other operating state.
The operation of a static memory cell is in contrast to other types of memory cells such as dynamic cells which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or “refreshing” to maintain this voltage for more than very short time periods.
A dynamic memory cell has no internal feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift toward intermediate or indeterminate voltages, resulting in loss of data. Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the four or more transistors typically required in a static memory cell. Because of the significantly different architectural arrangements and functional requirements of static and dynamic memory cells and circuits, static memory design has developed along generally different paths than has the design of dynamic memories. An SRAM cell is typically ten to twenty times larger than a DRAM cell and provides five to ten times greater performance than the DRAM counterpart, when such devices are built on conventional silicon single crystal substrates. It would be desirable to provide high speed yet dense SRAM memory cell constructions over a versatile substrate, such as, for example, glass, to extend application flexibility and to reduce cost.